View TMC2601_1704753.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary information preliminary information describes products that are not in full production at the time of printing. specifications are based on design goals and limited characterization. they may change without notice. contact fairchild semiconductor for current information. www.fairchildsemi.com features ? 0.6 m cmos technology ? single +5 v power supply ? 44 pin pqfp or plcc ? 0.5 w typical power dissipation ? 140-370 megabit/s data rate ? complies with the following digital video interface standards: C smpte 259mbit-serial 4:2:2 component (d1) C smpte 125mbit-parallel 4:2:2 component (d1) C smpte 244mbit-parallel 4*f sc ntsc composite (d2) ? accepts 8- or 10-bit ttl or cmos-compatible parallel data ? outputs differential pseudo-ecl serial data and clock ? byte sync on timing reference signal (trs) ? modulo - 2 division by g(x) = (x 9 +x 4 +1)*(x+1) scrambler ? phase-locked loop clock synthesizer ? transmitter jitter < 500 ps at 270 mb/s ? power saving feature on unused clock and data outputs applications ? encoder for 140 to 370 mb/s serial data ? serial transmission interface for: C video cameras 360 mb/s C 4:2:2 signals 270 mb/s C4* f sc pal 177 mb/s C 4* f sc ntsc 143 mb/s description the TMC2601 is a cmos integrated circuit which can serialize 8- or 10-bit parallel data streams, including smpte 125m, ccir 656, and smpte 244m. fixed functions include parallel- to-serial conversion and 10-fold clock frequency multiplication. the user may also enable sync (trs word) detection, data scrambling (x 9 +x 4 +1), and conversion of nrz serial data into nrzi format (x+1). using control bis fs 1-0 , the user may select a nominal operating frequency of 143, 177, 270, or 360mhz. the TMC2601 provides pseudo-ecl outputs: complemen- tary for the serial data and serial clock, single-ended for the regenerated parallel clock. it requires a single 5-volt supply and consumes less than 1/2 watt while driving 100-ohm loads. block diagram 65-2601-01 nrz to nrzi pll high speed clock synthesizer sync detect lock detect serial output output disable scram ref. clock 14 - 37 mhz reset pcko di0-di9 input parallet to serial converter 10 bit x 3 word shift register pecl buffer scrambler by-pass scrambler ? 10 sck sync detect sync detect disable sck disable plock vco center frequency select power on reset data rate select (fs1) output enable TMC2601 digital video serial transmission encoder 8- or 10-bit parallel data into serial format 140C370 mhz output frequency rev 1.00
TMC2601 product specification 2 preliminary information pin assignments pin descriptions pin name pin number type pin function description gnd 1 supply ground v dd 2 supply +5v supply sync det 3 ttl out trs detected flag. if and only if di 9-2 =ffh or 00h, flag does low on the following clock cycle. gnd 4 supply ground v dd 5 supply +5v supply sync det dis 6 ttl in trs formatter disable. when low, chip forces di 1- 0 to 00b if di 9-2 =00h and to 11b if di 9-2 =ff. when high, passes input data unaltered. di 0-9 7-16 ttl in bit-parallel input data di 0 is lsb in 10-bit mode lsb, di2 is lsb in 8-bit mode. di 9 is msb in all modes pck in 17 ttl in parallel clock input. rising edge strobes di9-0 into chip. gnd 18 supply ground pck out 19 ecl out parallel clock output. this pseudo-ecl signal is derived from the internal vco and maintains a constant phase relationship with pcki when the loop is locked. lock det 20 ttl out phase locked flag goes high when the loop is locked. v dd 21 supply +5v supply 65-2601-02 di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 di 9 pck in dout dout gnd fs 0 fs 1 nc nc nc nc gnd ddis sync det dis v dd gnd sync det v dd gnd gnd sck sck v dd v dd gnd pck out lock det v dd sckdis gnd reset gnd sss gnd v dd 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 TMC2601
product specification TMC2601 3 preliminary information note 1. these pins may be left open or ac coupled. do not dc couple to ground unless the corresponding output is to be disabled; logic 1 or high-z (due to internal pull up) enables the output and 0 disables it. sck dis 22 ttl in grounding this pin disables the serial clock output. 1 gnd 23 supply ground reset 24 ttl in when forced high, this pin (which has an internal pull-down) resets the part. gnd 25 supply ground sss 26 ttl in when high, this pin bypasses the scrambler and nrzi conversion blocks, providing direct serialization of the data. gnd 27 supply ground v dd 28 supply +5v supply ddis 29 ttl in grounding this pin disables the serial data output. 1 gnd 30 supply ground nc 34:31 nc may be grounded directly or via a resistor. fs 1-0 35-36 ttl in frequency select input. selects vco frequency range gnd 37 supply ground dout 38 ecl out differential pseudo-ecl serial data output requiring an external >100-ohm resistor to dout . dout 39 ecl out differential serial data output, compement of dout . v dd 40 supply +5v supply v dd 41 supply +5v supply sck 42 ecl out differential pseudo-ecl serial clock output, requiring external 100-ohm resistor to sck . sck 43 ecl out differential serial clock output, complement to sck . gnd 44 supply ground pin descriptions (continued) pin name pin number type pin function description
TMC2601 product specification 4 preliminary information functional description the TMC2601 serializer is a cmos integrated circuit which converts parallel data in a format such as smpte125m or smpte244m into a serial format, such as smpte 259m. it encodes 8- or 10-bit ttl-compatible parallel signals into serial differential pseudo-ecl signals at up to 370mb/s. it operates from a single 5v supply and is packaged in a 44-pin plcc. the internal functional blocks include the sync detector, data serializer, polynomial scrambler and nrz to nrzi con- verter, and 10-fold clock frequency multiplier. sync detector on each rising edge of pcki, the sync detector looks for combinations of all 1s or all 0s on pins di 9-2 . whenever it encounters one of these combinations, the sync detector drives sync det low on the next parallel clock cycle. if control sync det dis is low, it also overrides di 1-0 to match di 9-2 , such that 000 through 003 (hex) become 000, and 3fc through 3ff become 3ff, to comply with smpte259. polynomial scrambler this feedback shift register pseudorandomizes the incoming data, using the smpte-speci?ed ?xed polynomial x 9 + x 4 +1, thereby minimizing the dc component in the output stream. a second polynomial operator, cascaded with the ?rst and based on x+1, converts nrz data into nrzi, turn- ing any long sequences of 1s into series of transitions. when high, control sss bypasses these two blocks, allowing direct serialization of the incoming data. phase-locked loop the pll, which multiplies the clock frequency by 10, com- prises a phase detector, a charge pump, a loop ?lter, a vco, and a divide-by-ten counter. on each parallel clock cycle, the loop ?lter receives a charge proportional to the phase error and perturbs the vcos frequency appropriately. vco frequency selector the chip provides four nominal frequency ranges, selected by fs 1-0 , as follows: the lock detect circuit disables the serial data output when the loop is not locked, at which time the lock detect ?ag will be low. complementary serial data emerge on sdo and sdo , whereas the serial clock appears on sck and sck . to reduce system noise and to save power, user not needing the serial clock may disable it by grounding loopf/sck dis. the chip also provides a single-ended ecl parallel clock output, pcko, regenerated from the internal pll. fs 0 fs 1 nominal frequency (mhz) 0 0 270 (d1) 0 1 360 1 0 143 (ntsc d2) 1 1 177 (pal d2)
product specification TMC2601 5 preliminary information absolute maximum ratings notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range, and measured with respect to gnd. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current, flowing into the device. parameter min. typ. max. units power supply voltage, v dd -0.5 7.0 v digital inputs applied voltage 2 -0.5 v dd + 0.5 v forced current 3,4 -20.0 20.0 ma outputs applied voltage 2 -0.5 v dd + 0.5 v forced current 3,4 -3.0 6.0 ma short circuit duration (single output in high state to gnd) temperature operating, ambient 0 70 c junction 140 c storage -65 150 c lead soldering (10 seconds) 300 c vapor phase soldering (1 minute) 220 c operating conditions parameter min. typ. max. units v dd supply voltage 4.75 5.25 v v ih digital inputs, high 2.0 v v il digital inputs, low 0.8 v t s data setup (to pcki rising edge) 5 ns t h data hold (from pcki rising edge) 0 ns tpwh parallel clock pulse width high (pcki) 8 ns tpwl parallel clock pulse width low (pcki) 8 ns
TMC2601 product specification 6 preliminary information electrical characteristics parameter min. typ. max. units power consumption i dd 800 mw v ohs serial output high logic level, from v dd -0.875 -0.7 v v ols serial output low logic level, from v dd -1.8 -1.5 v v ohp ttl output high logic level 2.4 v v olp ttl output low logic level 0.5 v i ih ttl input high current -50 50 i il ttl input low current -50 50 switching characteristics parameter conditions min. typ. max. units f out output clock & bit rate r l =100 ohms 110 400 mhz v sd output data & clock amplitude, p-p 700 850 mv t jo output clock jitter 270mb/s 700 ps t d serial clock to data lag 1.4 ns sdo t r /t f serial data output rise/fall time 650 t lock lock time 25 f pckout parallel clock output frequency 11 40 pckout t r /t f parallel clock output rise/fall time 700 v pckout parallel clock output signal swing 950 t jpckout parallel clock output jitter 700
product specification TMC2601 7 preliminary information pcki data 9-0 dout, dout dout, dout t jo 80% 20% tf tr 65-2601-03 ts th 10/f out input timing output timing
TMC2601 product specification 8 preliminary information typical application circuit notes: all resistors in ohms, all capacitors in microfarads unless otherwise stated. *these components may be omitted, without affecting functionality. see text. **these resistors slow down fast input edges ( 500ps) and prevent the input signals from ringing. 65-2601-04 pd1 100 8 TMC2601 data 1 pd2 100 9 data 2 pd3 100 10 11 12 13 14 15 16 17 10k +5v 10k 0.1* 0.1* 820* 3.9k* 4k 4x0.1* 1* 36 35 29 22 +5 +5v test serial clock out serial data out 1m 19 42 100 34 nc nc nc nc vee 1,4 18,23 25,27 30,37 44 data 3 pd4 100 data 4 pd5 100 data 5 pd6 100 data 6 pd7 100 data 7 pd8 100 data 8 pd9 100 data 9 pck in 100 clock data rate select dip swtich (see truth table) fs0 fs1 pck-out creg skdis sck sck 43 pd0 **100 7 20 5k 10k 330 loop locked l.e.d. 2n4400 (optional) lock scram sync dis. (6x vcc) 26 2,5,21,28,40,41 6 6x100n +10 data 0 10pf 100 2* 33 3 32 4* 31 39 sd0 38 sd0 +5v
product specification TMC2601 9 preliminary information equivalent circuits and threshold levels figure 1. equivalent digital input circuit figure 2. equivalent digital output circuit figure 3. threshold levels for three-state measurements digital input v dd p n 27014c gnd v dd p n 27011c gnd digital output 7048c t ena 2.0v 0.8v t dis three-state outputs cs high impedance 0.5v 0.5v
TMC2601 product specification 10 preliminary information notes:
product specification TMC2601 11 preliminary information mechanical dimensions C 44-pin plcc package d e e a .165 .180 4.20 4.57 symbol inches min. max. min. max. millimeters notes e1 j d1 a a1 a2 b b1 d3/e3 j ?c ccc c lead coplanarity a1 .090 .120 2.29 3.04 a2 .020 .51 b .013 .021 .33 .53 d/e .685 .695 17.40 17.65 d1/e1 .650 .656 16.51 16.66 d3/e3 .500 bsc 12.7 bsc e .050 bsc 1.27 bsc j .042 .056 1.07 1.42 2 3 nd/ne 11 11 n44 44 ccc .004 0.10 b1 .026 .032 .66 .81 notes: 1. 2. 3. all dimensions and tolerances conform to ansi y14.5m-1982 corner and edge chamfer (j) = 45 dimension d1 and e1 do not include mold protrusion. allowable protrusion is .101" (.25mm)
preliminary information TMC2601 product specification preliminary information 8/30/99 0.0m 002 stock#ds30002601 1998 fairchild semiconductor corporation life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information product number temperature range screening package package marking TMC2601r2c 0 c to 70 c commercial 44-lead plcc 2601r2c

▲Up To Search▲

Price & Availability of TMC2601

	To Download TMC2601 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .